Figure 4.8. The optimized quantum full-subtractor.
4.3 Summary
This chapter presents the quantum full-adder and full-subtractor from the half-adder and half-subtractor circuits. The quantum costs of the adder and subtractor circuits are discussed for better understanding of the circuits.
Further reading
[1] Babu H M H, Islam M R, Chowdhury S M A and Chowdhury A R 2004 Synthesis of a full-adder circuit using reversible logic Proc. 17th Int. Conf. on VLSI Design (Mumbai) 2004 pp 757–60
[2] Babu H M H, Islam R, Chowdhury A R and Chowdhury S M A 2003 On the realization of reversible full-adder circuit Int. Conf. on Computer and Information Technology pp 880–3
[3] Babu H M H, Islam R, Chowdhury A R and Chowdhury S M A 2003 Reversible logic synthesis for minimization of full-adder circuit Proc. Euromicro Symp. on Digital System Design pp 50–4
[4] Babu H M H, Jamal L and Saleheen N 2013 An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder IEEE Int. SOC Conf. pp 98–103
[5] Cheng K-W and Tseng C-C 2002 Quantum full adder and subtractor Electron. Lett. 38 1343–4
[6] Cuccaro S A, Draper T G, Kutin S A and Moulton D P 2004 A new quantum ripple-carry addition circuit (arXiv: quant-ph/0410184)
[7] Khan M H A and Perkowski M A 2007 Quantum ternary parallel adder/subtractor with partially-look-ahead carry J. Syst. Archit. 53 453–64
[8] Monfared A T and Haghparast M 2016 Design of new quantum/reversible ternary subtractor circuits J. Circuit. Syst. Comp. 25 1650014
[9] Murali K V R M, Sinha N, Mahesh T S, Levitt M H, Ramanathan K V and Kumar A 2002 Quantum-information processing by nuclear magnetic resonance: experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system Phys. Rev. A 66 22313
[10] Takahashi Y 2009 Quantum arithmetic circuits: a survey IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92 1276–83
[11] Takahashi Y, Tani S and Kunihiro N 2010 Quantum addition circuits and unbounded fan-out Quantum Inf. Comput. 10 872–90
IOP Publishing
Quantum Computing
A pathway to quantum logic design
Hafiz Md Hasan Babu
Chapter 5
The quantum multiplexer and demultiplexer
In large-scale computing systems, it is necessary for a single line to carry two or more signals. One signal can be placed on one line at a time. However, the device which will allow us to select and place the signal we choose on a common line, is called a multiplexer (MUX). The purpose of a MUX is to select the input of any n inputs and feed that to one output line. The function of a demultiplexer (DEMUX) is the opposite to the function of the MUX.
5.1 The quantum multiplexer
This section presents the design of the quantum multiplexer. The multiplexer causes the transmission of a large number of information units over a smaller number of channels. Architecturally a digital multiplexer is a logic circuit that puts one of several inputs to a single output. A set of selected inputs controls the inputs. Generally a multiplexer has m inputs and n selected inputs where m=2n.
5.1.1 The quantum 2-to-1 multiplexer
A 2-to-1 multiplexer is the smallest unit of architecture of a quantum multiplexer. The characteristic function of a multiplexer is s0′I0+s0I1. A quantum Fredkin gate, as shown in figures 5.1(a) and (b), can be used as a 2-to-1 quantum multiplexer as it can map the characteristic function of a multiplexer.
Figure 5.1. The quantum Fredkin gate. (a) Quantum circuit of a quantum Fredkin gate. (b) Symbol of a quantum Fredkin gate.
Let I0 and I1 be the inputs and S0 be the selected input of a 2-to-1 multiplexer. When S0=0, then input I0 transmits to the output Y and when S0=1, then input I1 transmits to the output Y. Figure 5.2 shows the architecture of a quantum 2-to-1 multiplexer using a quantum Fredkin gate. The quantum cost and delay of this quantum 2-to-1 multiplexer are 5 and 5Δ, respectively. Moreover, the number of garbage outputs is two.
Figure 5.2. The quantum Fredkin gate as a quantum 2-to-1 multiplexer.
5.1.2 The quantum 4-to-1 multiplexer
The quantum 4-to-1 multiplexer has four inputs, two select lines, and one output. Figure 5.3 illustrates the design of a quantum 4-to-1 multiplexer, where I0, I1, I2, and I3 are the inputs, and S0 and S1 are the select lines. The bit combination of select lines controls the function of a 4-to-1 multiplexer, as presented in table 5.1. Three quantum Fredkin gates are used in this design. Thus the quantum cost of the quantum 4-to-1 multiplexer is 15 and the delay is 15Δ in the logic circuits, respectively; whereas the number of garbage outputs is five.
Figure 5.3. The quantum 4-to-1 multiplexer.
Table 5.1. Function of S0 and S1 select lines.
| S 0 | S 1 | Output(O) |
|---|---|---|
| 0 | 0 | I 0 |
| 0 | 1 | I 1 |
| 1 | 0 | I 2 |
| 1 | 1 | I 3 |
5.1.3 The quantum 2n-to-1 multiplexer
Figure 5.4 shows the design of a quantum 8-to-1 multiplexer. As the consequence of the design of quantum multiplexers, a 2n-to-1 multiplexer can be constructed