∣E1〉=∣A1〉⊙∣B1〉∣G1〉=∣A1B1¯〉3∣L1=∣A1¯B1〉.(3.3)
Then the outputs of the MQC circuit (∣E1〉, ∣G1〉, ∣L1〉) and the rest of the qubits (∣A0〉, ∣B0〉) are used as inputs to the next circuit which is the RQC circuit. This circuit produces the final outputs
∣AGB0〉=∣G1〉+∣E1〉.∣A0(B0)〉∣ALB0〉=∣L1〉+∣E1〉.∣(A0)B0〉∣AEB0〉=∣AGB0〉⊙∣ALB0〉.(3.4)
Figure 3.6. The two-qubit quantum comparator circuit. Reproduced with permission from [2]. Copyright 2017 IEEE.
Similarly, an n-qubit quantum comparator circuit can be constructed using one MQC circuit and maximum (n − 1) RQC circuits or minimum ((n/2) − 1) RQC to perform the greater than, less than, and equality operations. In figure 3.7, the detailed quantum circuit for an n-qubit quantum comparator is shown.
Figure 3.7. The n-qubit quantum comparator circuit. Reproduced with permission from [2]. Copyright 2017 IEEE.
3.4 Summary
This chapter presents the design methodology for a noble quantum n-qubit comparator using a fast comparison technique. The time complexity of the comparison technique is O(logn) where n is the number of qubits. The comparator was constructed in two steps. First, bit comparisons for greater than and less than operations were performed in parallel. Then bit comparison for the equality operation was performed. The quantum comparator circuit can be used in designing different quantum circuits, such as quantum processing units, complex arithmetic circuits, and communication systems. Thus the design which has been shown in this chapter should help the reader understand the next three chapters better. In addition, the concept of designing a quantum bit string comparator will help in designing the quantum subtraction, multiplier, divider, and adder circuits.
Further reading
[1] Barwad R 2015 The characteristics of comparator Polytechnic Hub http://www.polytechnichub.com/characteristics-comparator/ (Accessed: 5 December 2018)
[2] Babu H M H, Jamal L, Dibbo S V and Biswas A K 2017 Area and delay efficient design of a quantum bit string comparator 2017 IEEE Computer Society Annual Symp. on VLSI (Piscataway, NJ: IEEE) pp 51–6
[3] Das J C and De D 2016 Reversible comparator design using quantum dot-cellular automata IETE J. Res. 62 323–30
[4] Dibbo S V, Babu H M H and Jamal L 2016 An efficient design technique of a quantum divider circuit IEEE Int. Symp. on Circuits and Systems (ISCAS) (Piscataway, NJ: IEEE) pp 2102–5
[5] Nielsen M A and Chuang I L 2000 Quantum Computation and Quantum Information 10th edn (Leiden: Cambridge University Press)
[6] Parida D 2010 A novel high speed CMOS comparator with low power dissipation and low offset PhD Thesis
[7] Phaneendra P S, Vudadha C, Sreehari V and Srinivas M B 2014 An optimized design of reversible quantum comparator 27th Int. Conf. on VLSI Design and 13th Int. Conf. on Embedded Syst. (Piscataway, NJ: IEEE) pp 557–62
[8] Saravanakumar N, NirmalKumar A, Nandhakumar A and KanyaKumari G E 2013 ASIC implementation of low power area efficient folded binary comparator Int. J. Sci. Eng. Technol. 5 4582
IOP Publishing
Quantum Computing
A pathway to quantum logic design
Hafiz Md Hasan Babu
Chapter 4
The quantum adder and subtractor
In circuit design the adder and subtractor are the circuits that are capable of adding or subtracting numbers. In this chapter quantum adder, namely half-adder and full-adder, circuits and subtractor, namely half-subtractor and full-subtractor, circuits are presented with their quantum representations.
4.1 The quantum adder
An adder is a circuit in electronics that implements the addition of numbers. In many computers and other types of processors, adders are used to calculate addition and similar operations in the arithmetic logic unit (ALU) and also in other parts of processors. These can be constructed for many numerical representations such as excess-3 or binary coded decimal. Adders are classified into two types: half-adder and full-adder. The half-adder circuit has two inputs, A and B, which add two input digits and generate a carry and a sum. The full-adder circuit has three inputs, A, B, and C, which add the three input numbers and generate a carry and a sum.
Table 4.1 is the truth table of a half-adder. From this table, we can obtain the half-adder circuit’s outputs which are
Sum=A⊕BCarry=AB.
Table 4.1. The truth table of the half-adder.
| A | B | Carry | Sum |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
The output equations of the half-adder can be mapped with a quantum Peres gate, as shown in figure 4.1, and the quantum half-adder can be obtained by putting C = 0, which is illustrated in figure 4.2. The quantum cost of the quantum half-adder is 4 and the delay is 4Δ.
Figure 4.1. The quantum Peres gate.
Figure 4.2. The quantum Peres gate as a quantum half-adder.
4.1.1 The quantum full-adder
Table 4.2 is the truth table of a full-adder. From this table we can obtain the output of the full-adder circuit:
Sum=A⊕B⊕CinCarry=(A⊕B)Cin⊕AB.
Table 4.2. The truth table of the full-adder.