21 8 Conclusion to Design for Excellence: Bringing It All Together 8.1 Design for Excellence (DfX) in Electronics Manufacturing 8.2 Chapter 2: Establishing a Reliability Program 8.3 Chapter 3: Design for Reliability (DfR) 8.4 Chapter 4: Design for the Use Environment: Reliability Testing and Test Plan Development 8.5 Chapter 5: Design for Manufacturability 8.6 Chapter 6: Design for Sustainability 8.7 Chapter 7: Root Cause Problem Solving, Failure Analysis, and Continual Improvement Techniques
22 Index a b c d e f g h I J K l m n o p q r s t u v w Z
List of Tables
1 Chapter 2Table 2.1 Common quality and reliability issues.
2 Chapter 3Table 3.1 Diurnal temperature for Phoenix, Arizona.Table 3.2 Lead‐free HASL challenges.Table 3.3 Laminate material selection.Table 3.4 ECM risk guidelines.Table 3.5 Deliquescence characteristics.Table 3.6 Contaminant cleanliness limits.Table 3.7 Conformal coating selection.Table 3.8 Potting definitions.
3 Chapter 4Table 4.1 Climate in Death Valley, CA.Table 4.2 MIL‐STD‐810 vibration environments.Table 4.3 Product environment conditions.
4 Chapter 5Table 5.1 MSL levels.Table 5.2 Copper weight.Table 5.3 Sources of contaminants.Table 5.4 Soldering process DPMM.
5 Chapter 6Table 6.1 Storage Options Summary.Table 6.2 Failure modes of stored electronic components.Table 6.3 Counterfeit risk and cost.
6 Chapter 7Table 7.1 RCA method effort comparison.
List of Illustrations
1 Chapter 2Figure 2.1 Reliability tools across the design and development process.Figure 2.2 Block diagram for a simple fuel system.Figure 2.3 Parallel brake system.
2 Chapter 3Figure 3.1 Costs committed vs. money spent.Figure 3.2 Concurrent engineering flow.Figure 3.3 Reliability physics in the design phase.Figure 3.4 Classic bathtub curve.Figure 3.5 Capacitor susceptibility to wearout and breakdown.Figure 3.6 Variation in shipping container temperature.Figure 3.7 Reliability physics models.Figure 3.8 Hardware design process.Figure 3.9 Hardware design process feedback loop.Figure 3.10 Deep integration with existing simulation workflows.Figure 3.11 Initial parts placement.Figure 3.12 Thermal data.Figure 3.13 Out‐of‐plane displacement.Figure 3.14 Part selection: BOM creation flow.Figure 3.15 ESD entry vectors.Figure 3.16 Expansion and contraction behavior.Figure 3.17 Images of solder coarsening.Figure 3.18 Tin whiskers.Figure 3.19 Tin whisker intermetallic formation.Figure 3.20 Detailed geometry and mesh of traces and vias.Figure 3.21 Detailed view of high‐ and low‐stress pads.Figure 3.22 Immersion silver galvanic etching.Figure 3.23 Champagne voiding.Figure 3.24 Creep corrosion.Figure 3.25 Compression on a PTH from ICT.Figure 3.26 PTH barrel crack.Figure 3.27 Conductive anodic filament formation.Figure 3.28 Conductive anodic filament example.Figure 3.29 Hollow fiber example.Figure 3.30 Strain level from a 50 G mechanical shock.Figure 3.31 Example of excessive strain.Figure 3.32 Reduced strain after mount points are added.Figure 3.33 Corner staking, edge bonding, and underfill.Figure 3.34 Pad cratering cross