Part II Quantum fault tolerance
17 Quantum fault-tolerant circuits
17.1 The need for quantum fault-tolerant circuits
17.2 The fault-tolerant quantum adder
17.2.1 The fault-tolerant full-adder
17.3 The fault-tolerant multiplier
17.3.1 The fault-tolerant signed multiplier
17.4 The quantum fault-tolerant integer divider
17.4.1 The restoring division algorithm
17.4.3 The conditional addition operation module
17.4.4 Quantum restoring integer division circuitry
Part III Quantum-dot cellular automata
18 Quantum-dot cellular automata
18.1 Fundamentals of QCA circuits
18.3 Information and data propagation
18.4 Basic QCA elements and gates
18.5.1 Special cell arrangements and symmetric cells
18.5.3 Majority voter clock zones
19 QCA adder and subtractor
19.2 The QCA half-adder and half-subtractor
19.3 The QCA full-adder and full-subtractor
19.3.1 Implementation of the full-adder and full-subtractor
20 The QCA multiplier and divider
20.1.1 Multiplication networks
20.1.2 QCA multiplication networks
20.2.1 The non-restoring binary divider
21 QCA asynchronous and synchronous counters
21.1.1 The dual-edge triggered J-K flip-flop
21.1.2 The design of dual-edge triggered J-K flip-flop
21.1.3 The asynchronous backward counter
21.2.1 QCA synchronous counters
22 The QCA decoder and encoder
22.2.1 The QCA turbo encoder design