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Digital System Design using FSMs
A Practical Learning Approach
Peter D. Minns
Formerly at Northumbria University Newcastle upon Tyne, UK
This edition first published 2021
© 2021 John Wiley & Sons Ltd
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Library of Congress Cataloging‐in‐Publication Data
Name: Minns, Peter D., author.
Title: Digital system design using FSMs : a practical learning approach / Peter D. Minns.
Description: Hoboken, NJ : Wiley, 2021. | Includes bibliographical references and index.
Identifiers: LCCN 2021015256 (print) | LCCN 2021015257 (ebook) | ISBN 9781119782704 (hardback) | ISBN 9781119782711 (adobe pdf) | ISBN 9781119782728 (epub)
Subjects: LCSH: Sequential machine theory. | Digital electronics.
Classification: LCC QA267.5.S4 M56 2021 (print) | LCC QA267.5.S4 (ebook) | DDC 621.381501/51135–dc23
LC record available at https://lccn.loc.gov/2021015256 LC ebook record available at https://lccn.loc.gov/2021015257
Cover Design: Wiley
Cover Image: (inset) Image by Peter Minns, (background) © Govindanmarudhai/Getty Images
Preface
This book is, in large part, a development of FSM‐Based Digital Design using Verilog HDL (Minns and Elliott 2008), a book I wrote with Ian Elliott. It is rather unusual in that it forms a linear programmed learning text in all chapters to help readers learn on their own.
The intention in this current version is to make use of programmed learning methods in which the chapters are made up of frames that must be read in a sequential manner. It is hoped that the book will help readers in their study of the material. There is also new content in Chapter 6, Appendix A5, and Appendix A6, as well as consideration of unused states in finite state machines (FSMs).
It is assumed that the reader has a good understanding of Verilog HDL; however, the interested reader will find that Chapters 6, 7, and 8 of Minns and Elliott (2008) provide a very good account of Verilog HDL.