Multi-Processor System-on-Chip 1. Liliana Andrade. Читать онлайн. Newlib. NEWLIB.NET

Автор: Liliana Andrade
Издательство: John Wiley & Sons Limited
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Жанр произведения: Программы
Год издания: 0
isbn: 9781119818281
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the total number of cycles on a single RISC-V core is 1.5x8.2 = 12.3 Mcycles.

      Table 1.4. Performance data for the CIFAR-10 CNN graph

Layer type ARC EM9D [ Mcycles ] Processor A [ Mcycles ] Processor B (RISC-V ISA) [ Mcycles ]
0 Permute 0.01
1 Convolution 1.63 6.78
2 Max Pooling 0.14 0.34
3 Convolution 3.46 9.25
4 Avg Pooling 0.09 0.09
5 Convolution 1.76 4.88
6 Avg Pooling 0.07 0.04
7 Fully-connected 0.03 0.02
8 Fully-connected 0.001
Total 7.2 21.4 12.3

      From Table 1.4, we conclude that the ARC EM9D processor spends 3x fewer cycles than processor A and 1.7x fewer cycles than the RISC-V core (processor B) for the same machine learning inference task, without using any specific accelerators. Thanks to the good cycle efficiency, the ARC EM9D processor can be clocked at a low frequency, which helps to save power in a smart IoT edge device.

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