Figure 11.1 Three typical earthing networks in low‐voltage systems.
Figure 11.2 Generic equivalent circuit for analyzing leakage currents.
Figure 11.3 Equivalent circuit for analyzing leakage current of a grid‐tied converter with a common AC and DC ground.
Figure 11.4 A conventional half‐bridge inverter.
Figure 11.5 A transformerless PV inverter.
Figure 11.6 Controller for the neutral leg.
Figure 11.7 Controller for the inverter leg.
Figure 11.8 Real‐time simulation results of the transformerless PV inverter in Figure 11.5(a).
Figure 12.1 STATCOM connected to a power system.
Figure 12.2 A typical two‐axis control strategy for a PWM based STATCOM using a PLL.
Figure 12.3 A synchronverter based STATCOM controller.
Figure 12.4 Single‐line diagram of the power system used in the simulations.
Figure 12.5 Detailed model of the STATCOM used in the simulations.
Figure 12.6 Connecting the STATCOM to the grid.
Figure 12.7 Simulation results of the STATCOM operated in different modes.
Figure 12.8 Transition from inductive to capacitive reactive power when the mode was changed at t = 3.0 s from the Q‐mode to the V‐mode.
Figure 12.9 Simulation results of the STATCOM operated with a changing grid frequency.
Figure 12.10 Simulation results of the STATCOM operated with a changing grid voltage.
Figure 12.11 Simulation results with a variable system strength.
Figure 13.1 Per‐phase diagram with the Kron‐reduced network approach.
Figure 13.2 Phase portraits of the controller.
Figure 13.3 The controller to achieve bounded frequency and voltage.
Figure 13.4 E+ surface (upper) and E− surface (lower) with respect to Ps and Qs.
Figure 13.5 Illustration of the areas characterized by E+ lines and E− lines.
Figure 13.6 Illustration of the area where a unique equilibrium exists.
Figure 13.7 Real‐time simulation results comparing the original (SV) with the improved self‐synchronized synchronverter (improved SV).
Figure 13.8 Phase portraits of the controller states in real‐time simulations.
Figure 14.1 The controller of the original synchronverter.
Figure 14.2 Active power regulation in a conventional synchronverter after decoupling.
Figure 14.3 Properties of the active power loop of a conventional synchronverter with Xpu = 0.05, ωn = 100π rad s−1, and α = 0.5%.
Figure 14.4 VSM with virtual inertia and virtual damping.
Figure 14.5 The small‐signal model of the active‐power loop with a virtual inertia block Hv(s).
Figure 14.6 Implementations of a virtual damper.
Figure 14.7 A VSM in a microgrid connected to a stiff grid.
Figure 14.8 Normalized frequency response of a VSM with reconfigurable inertia and damping.
Figure 14.9 Effect of the virtual damping (Jv = 0.2 s).
Figure 14.10 A microgrid with two VSMs.
Figure 14.11 Two VSMs operated in parallel with Jv1 = Jv2 = 1 s.
Figure 14.12 Two VSMs operated in parallel with Jv1 = 0.5 s and Jv2 = 1 s.
Figure 14.13 Simulation results under a ground fault with Jv = 0.1, 0.3, 0.5, 1 s.
Figure 14.14 Experimental results with reconfigurable inertia and damping.
Figure 14.15 Experimental results from the original synchronverter for comparison.
Figure 14.16 Experimental results showing the effect of the virtual damping with Jv = 0.2 s.
Figure 14.17 Experimental results when two VSMs with the same inertia time constant are in parallel operation.
Figure 14.18 Experimental results when two VSMs with different inertia time constants operated in parallel.
Figure 14.19 Experimental results when the two VSMs operated as the original SV in parallel operation with τω1 = τω2 = 1 s for comparison.
Figure 15.1 Block diagrams of a conventional PLL.
Figure 15.2 Enhanced phase‐locked loop (EPLL) or sinusoidal tracking algorithm (STA).
Figure 15.3 Power delivery to a voltage source through an impedance.
Figure 15.4 Conventional droop control scheme for an inductive impedance.
Figure 15.5 Conventional droop control strategies.
Figure 15.6 Linking the droop controller in Figure 15.4(b) and the (inductive) impedance.
Figure 15.7 Droop control strategies in the form of a phase‐locked loop.
Figure 15.8 The conventional droop controller shown in Figure 15.4(a) after adding two integrators and a virtual impedance.
Figure 15.9 The synchronization capability of the droop controller shown in Figure 15.8.
Figure 15.10 Connection of the droop controlled inverter to the grid.
Figure 15.11 Regulation of the grid frequency and voltage in the droop mode.
Figure 15.12 Robustness of synchronization against DC‐bus voltage changes.
Figure 15.13 System response when the operation mode was changed.
Figure 16.1 A single‐phase inverter.
Figure 16.2 Controller to achieve a resistive output impedance.
Figure 16.3 Controller to achieve a capacitive output impedance.
Figure 16.4 Typical output impedances of L‐, R‐, and C‐inverters.
Figure 16.5 Two R‐inverters operated in parallel.
Figure 16.6 Conventional droop control scheme for R‐inverters.
Figure 16.7 Experimental results: two R‐inverters in parallel with conventional droop control.
Figure 16.8 Robust droop controller for R‐inverters.
Figure